Ferroelectric crystals, including the PLZT, PZT, PLT, etc. types of material are well known as perovskites that can be polarized in one direction, or the other, and can maintain the polarization states in the absence of a voltage applied thereto. When the ferroelectric material is incorporated as a dielectric between capacitor plates, the polarization states can be stored, and remain in the polarization state without any voltage applied across the capacitor plates. When such type of capacitors are implemented in memory cells, a nonvolatile storage device is achieved. The combination of ferroelectric capacitors in a memory array allows a random access and high speed memory to be realized, where the data is stored in polarization states in a nonvolatile manner.
The use of ferroelectric material in semiconductor memories is not without various disadvantages. Ferroelectric and silicon material are not directly compatible, as the latter tends to become degraded or contaminated, unless various precautions are taken during the fabrication of the memory. U.S. Pat. No. 5,046,043 by Miller et al. discloses techniques for overcoming the problem of integrating ferroelectric material with silicon material. Another problem with ferroelectric material is that with high speed operation, such as occurs in semiconductor memories, the time period in which a voltage is actually applied across the plates of a ferroelectric capacitor is very small, often in nanoseconds, and thus the ferroelectric material does not become completely polarized during the write cycle. By this, it is meant that in high speed write cycles all or substantially all of the domains in the ferroelectric material do not become reoriented by the influence of the electric field applied across the ferroelectric material. It is a well known phenomenon that the longer the polarization voltage is applied across the ferroelectric material, the more complete the polarization of the domains in the material.
U.S. Pat. No. 4,893,272 discloses a technique for increasing the effective time period in which a polarization voltage is applied to one plate of the ferroelectric capacitor, although the actual polarizing pulse occurs in a very short period of time. The technique for writing a polarization state in the noted patent is to apply a drive pulse to the plate line of the memory cell, apply a word line signal to drive a switching transistor into a conductive state to connect the ferroelectric capacitor between the plate line and a bit line, and then remove the word line drive before removing the plate line signal to thereby isolate the voltage on the one capacitor plate. In this manner, the isolated voltage on the one capacitor plate tends to maintain a voltage across the ferroelectric material and improve retention of the polarization state, even after the plate line signal has been removed. However, the severe disadvantage of the method and structure disclosed in the noted patent is that only one polarization state is affected by the isolated voltage which is held in the capacitor plate for a longer period of time, while the other polarization state must achieve polarization during the short period of time in which the polarizing pulse is applied to the ferroelectric material, as the other plate of the capacitor is not isolated from the plate line. Thus, for all the memory cells in the patent that have been written to the one polarization state, the retention thereof is enhanced, while the other memory cells storing the other polarization state are subject to the traditional polarization retention problems. It can be appreciated that as the access speeds of memories become shorter, the polarization retention problem is exacerbated.
Another problem inherent with the polarization retention technique described in the U.S. Pat. No. 4,893,272 is that with only one plate of the ferroelectric capacitor isolated from the bit line, semiconductor substrate currents can be generated by the occurrence of switching signals on the nonisolated plate. In practice, this can present a substantial problem as the nonisolated plate of the ferroelectric capacitor is connected by a line to many other ferroelectric capacitors in the array. Hence, should zero volts be initially stored on the isolated ferroelectric capacitor plate with 5 volts applied to the nonisolated plate, and thereafter when the nonisolated plate is driven to zero volts, the isolated plate must necessarily experience a negative voltage of -5 volts. This situation can cause the generation of substrate currents which can lead to latch-up and other problems. This problem is especially serious when utilizing CMOS type of logic circuits.
From the foregoing, it can be seen that a need exists for a technique of providing symmetrical and balanced polarization states in a ferroelectric capacitor, irrespective of which state is to be stored. A further need exists for a technique of providing a high reliability memory where the polarization retention is enhanced by driving the ferroelectric capacitor with a very short pulse, and providing a voltage across both plates of the capacitor for an effectively longer period of time than the write cycle.